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[VHDL-FPGA-Verilog] usb3.0

Description: USB的VHDL程序通过验证准确无误大家看看 看吧-USB through the VHDL program to verify the accuracy of all look at and see and see
Platform: | Size: 3155968 | Author: sunjia | Hits:

[VHDL-FPGA-Verilog] FPGA_VHDL_code

Description: FPGA学习非常珍贵的资料，包括USB、UART、I2C、Ethernet、VGA、CAN等总线的VHDL实现，可以直接应用于实际项目中。需要的请下载。 -FPGA to learn very valuable information, including USB, UART, I2C, Ethernet, VGA, CAN bus, such as VHDL to achieve, can be directly applied to actual projects. Need to download.
Platform: | Size: 1605632 | Author: suzhenwei | Hits:

[Embeded-SCM Develop] EXampleofFPGA

Description: FPGA的实验源程序，包括USB、UART、combus、I2c等，很适合学习使用-The use of FPGA tutorials, including USB, UART, combus, I2c and so on, very suitable for learning to use
Platform: | Size: 3063808 | Author: 王张刚 | Hits:

[VHDL-FPGA-Verilog] FPGAUSB

Description: FPGA的USB接口设计，包括各种驱动文档，十分方便好用-FPGA design of the USB interface, including document-driven, very easy-to-use
Platform: | Size: 3417088 | Author: 苏子 | Hits:

[VHDL-FPGA-Verilog] ActelFPGA_HE_ApplicationNote

Description: 在手持式设备的应用中(包括智能电话、相机和 MP3 播放器)，用户大多考虑低功耗、 小尺寸，整个系统中除了处理器外，往往需要提供多种通信接口与存储器接口，用于实现对 硬盘、SD 卡、CF 卡以及 USB 的通信等，用 FPGA 来实现这些接口将会是一种理想的解决 方案。本方案采用 Actel 低功耗的 IGLOO 系列作为处理器(PXA270 或 ARM)的桥接器件和 设备控制器，不仅能够大大简化处理器设计的复杂度，而且 IGLOO 的超低功耗 (最小 5μ W)以及超小封装(4mm*4mm)给手持式产品带来了前所未有的。 -In the application of handheld devices (including smart phone, camera and MP3 players), users are considering low-power, Small size, the whole system in addition to the processor, usually need to provide various communication interface and storage interface, used to implement Hard disk, SD card, CF card and USB communication, etc, to realize these interfaces with FPGA will be an ideal solution Scheme. The scheme adopts Actel IGLOO of low power consumption PXA270 processor (series as a bridge or ARM) devices and Equipment controller, can not only greatly simplified, and the complexity of the processor design IGLOO of low power consumption (minimum 5 mu W) and small package (4mm 4mm*) for handheld product has brought an unprecedented.
Platform: | Size: 242688 | Author: zxx359654879 | Hits:

[SCM] 68013datasheet

Description: 一个非常不错的描述68013芯片数据手册，希望给大家分享-A very good description of 68013 chip data sheet, hoping to share with you
Platform: | Size: 516096 | Author: 苏清波 | Hits:

[VHDL-FPGA-Verilog] USB2.0

Description: usb2.0 fpga程序 用vhdl语言编写 quartus环境实现 -usb2.0 fpga using vhdl language program quartus environment to achieve
Platform: | Size: 3567616 | Author: PETER | Hits:

[VHDL-FPGA-Verilog] xtp051_sp601_schematics

Description: Xilinx公司最新的Spartan 6系列FPGA所用的开发板电路图，详尽包括了电源、IO、外设、USB等部分的内容，极具有参考价值，另外还有一个USB芯片 68013所使用的HEX文件可供下载-Xilinx' s new Spartan 6 Series FPGA development board used in circuit detail, including the power, IO, peripherals, USB and some other content, most with a reference value, in addition to a USB chip, 68013 using HEX file available for download
Platform: | Size: 311296 | Author: Frank | Hits:

[VHDL-FPGA-Verilog] VerilogFPGAUSB

Description: 用Verilog（FPGA）实现USB源代码大家-Using Verilog (FPGA) source code we look to achieve USB
Platform: | Size: 153600 | Author: yang | Hits:

[VHDL-FPGA-Verilog] DE2_TV

Description: 友晶公司DE2开发板的TV示例完整源代码 FPGA Cyclone-Friends of the crystal of TV company DE2 development board complete source code for FPGA CycloneII sample
Platform: | Size: 4076544 | Author: caizuhong | Hits:

[SCM] usb_wr_firmware

Description: CY7C68013固件 FPGA把数据通过usb写入pc slave 模式 使用 EP6 -USB:FPGA write data to PC by USB change from cypress example slave mode and use EP6 bulkloop.c firmware based on the firmware frameworks. Building this example requires the full version of the Keil Tools.
Platform: | Size: 165888 | Author: shenjianfei | Hits:

[USB develop] usbFPGAconnect

Description: 该例程是PC机通过FX2-CY7C68013-A的USB2.0控制芯片与FPGA实现通信。其中的工程和代码包括PC机上的USB固件程序、驱动程序、上位机程序，FPGA上的VERILOG通信程序。-The routine is a PC, through the FX2-CY7C68013-A of the USB2.0 controller chip and the FPGA to achieve communication. One of the projects and code, including PC, the USB firmware, drivers, FPGA' s Communication Program
Platform: | Size: 7154688 | Author: 梁先国 | Hits:

[VHDL-FPGA-Verilog] CY7c68013_fpga_write_sram

Description: FPGA和USB经行通讯的源代码，很好很强大，希望对大家有用，-FPGA and the USB line of communication through the source code, nice and strong, we want to be useful, haha
Platform: | Size: 269312 | Author: 马秀成 | Hits:

[VHDL-FPGA-Verilog] Oscilloscope

Description: The design is designed partly in VHDL, partly in schematic drawings and targets a Xilinx Spartan-2E FPGA. However, since the design was tailored specifically for the aforementioned boards it is highly unlikely that it can be ported to other hardware. The circuits were designed on a Windows XP using the Xilinx WebPack 6.2 tool. The transfer of the design to the FPGA was carried out either with the Xilinx Impact tool through a parallel JTAG cable or with the Digilent Export utility through a USB JTAG cable.
Platform: | Size: 1854464 | Author: sami | Hits:

[Embeded-SCM Develop] ucecho

Description: Working example for Java application to connect to USB device CY7C68013A using an FPGA. FPGA automaticcaly writes data to be fetched from USB device. Java application runs speed test (upto 30 MB/s) and checks quality of data.
Platform: | Size: 403456 | Author: abel | Hits:

[VHDL-FPGA-Verilog] bmp

Description: Quick BMP-Test for CY7C68013A-USb device. Ready to run program for FPGA.
Platform: | Size: 22528 | Author: abel | Hits:

[VHDL-FPGA-Verilog] 1

Description: 基于FPGA的USB接口设计，实现了USB与FPGA的通信-USB interface to FPGA-based design, implementation of the USB communication with the FPGA
Platform: | Size: 1024 | Author: zhao | Hits:

[VHDL-FPGA-Verilog] spart6_usb_rw_example

Description: 这是USB芯片CY68013和FPGA互连的读写的实例代码，sparten6是新的FPGA平台，对需要使用新的平台的朋友，有一定的帮助。-This is the USB chip and the FPGA interconnect CY68013 read the example code, sparten6 a new FPGA platform, the platform on the need to use the new friends, have some help.
Platform: | Size: 2048 | Author: leo | Hits:

[VHDL-FPGA-Verilog] fpga-usb

Description: fpga and usb in vhdl. good to know
Platform: | Size: 220160 | Author: Mirza | Hits:

[VHDL-FPGA-Verilog] ISE_lab5

Description: 使用VHDL 语言编写7 段数码管显示程序， 掌握数码管的驱动方法。使用USB 电缆或并口下载线下载逻辑电路到FPGA，并 调试电路使其正常工作。-Using the VHDL language 7-segment display program, for digital control of the driving method. Using the USB cable or parallel port download cable to download logic to FPGA, and debug the circuit to work properly.
Platform: | Size: 2048 | Author: | Hits:
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